// Copyright (C) 1953-2022 NUDT
// Verilog module name - slave_node_process
// Version: V4.1.0.20221206
// Created:
//         by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module slave_node_process
#(
parameter clk_period = {8'd8,41'h0}//8ns
)
(
    i_clk  ,
    i_rst_n,
    
    i_tsnnic_or_tsnswitch                 ,//1:tsnnic.  0:tsnswitch
    i_sync_step_mode                      ,

    iv_link_delay                         ,
	iv_link_delay_port_id                 ,
	i_link_delay_wr                       ,
	
	iv_csrateoffset_localnode             ,
    ov_csrateoffset_previousnode          ,
    o_csrateoffset_previousnode_wr        ,
	iv_offset_threshold                   ,
	
    iv_data                               ,
	i_data_wr                             ,
    iv_tsmp_subtype                       ,

    //ov_cumulativescaledrateoffset         ,
    //o_cumulativescaledrateoffset_wr       ,
    ov_frequency_cor         ,
    
    ov_gm_timestamps         ,
    ov_correctfield_time     ,
    ov_local_cnt_rx          ,
    ov_sync_correctfield_time,
    ov_sync_link_delay       ,
    o_time_info_valid        ,
    
    ov_clk_set             ,
    o_clk_set_wr           ,
    ov_current_local_count ,
    ov_current_sync_clk    ,

    iv_frequency_cor                      ,
	i_frequency_cor_wr                    ,
    ov_sync_clk                           ,
    o_local_cnt_rst                       ,
    ov_local_count                        ,
	o_sync_ok                             ,
	o_sync_ok_wr                          ,
	ov_offset                             ,
	o_offset_wr                           ,
	ov_offset_abnormal_cnt                ,
	o_sync_result_wr                      ,
	
	ov_data                               ,
	o_data_wr                             
);

// I/O
// clk & rst
input                   i_clk;
input                   i_rst_n; 

input                   i_tsnnic_or_tsnswitch;
(*MARK_DEBUG="true"*)input                   i_sync_step_mode     ;
// pkt input                      ;
input      [27:0]       iv_link_delay     ;
input      [4:0]        iv_link_delay_port_id;
input                   i_link_delay_wr      ;

input      [31:0]       iv_csrateoffset_localnode      ;
output     [31:0]       ov_csrateoffset_previousnode   ;
output                  o_csrateoffset_previousnode_wr ;

input      [11:0]       iv_offset_threshold;

input      [48:0]       iv_frequency_cor       ;
input                   i_frequency_cor_wr     ;

(*MARK_DEBUG="true"*)input	    [8:0]	     iv_data        ;
(*MARK_DEBUG="true"*)input	         	     i_data_wr      ;
input      [7:0]        iv_tsmp_subtype;
// pkt output to NMA
//output     [31:0]	    ov_cumulativescaledrateoffset        ;
//output    	        o_cumulativescaledrateoffset_wr      ;

output     [79:0]       ov_sync_clk             ;
output     [39:0]       ov_local_count          ; 
output                  o_local_cnt_rst         ;  

output          	    o_sync_ok                      ;
output                  o_sync_ok_wr                   ;
output     [12:0]	    ov_offset                      ;
output                  o_offset_wr                    ;
output     [15:0]	    ov_offset_abnormal_cnt         ;
output    	            o_sync_result_wr               ; 
	      
(*MARK_DEBUG="true"*)output     [8:0]	ov_data        ;
(*MARK_DEBUG="true"*)output    	        o_data_wr      ;

output     [48:0]       ov_frequency_cor       ;  

output     [79:0]	    ov_gm_timestamps        ;
output     [63:0]	    ov_correctfield_time    ;
output     [39:0]	    ov_local_cnt_rx         ;
output     [63:0]       ov_sync_correctfield_time;
output     [27:0]       ov_sync_link_delay       ;
output      	        o_time_info_valid       ; 

output     [95:0]	    ov_clk_set             ;
output    	            o_clk_set_wr           ;
output     [39:0]       ov_current_local_count ;
output     [95:0]       ov_current_sync_clk    ;

wire       [8:0]        wv_data_lda2other        ;
wire      	            w_data_wr_lda2other      ; 

wire       [63:0]	    wv_sync_correctfield_time_lda2tex ;
wire       [27:0]	    wv_sync_link_delay_lda2tex        ;

wire       [120:0]      wv_sync_clk_ctc2ccc             ;
assign   ov_sync_clk =  wv_sync_clk_ctc2ccc[120:41];             
link_delay_accumulate link_delay_accumulate_inst
(
    .i_clk                                 (i_clk                         ),
    .i_rst_n                               (i_rst_n                       ),
    
    .i_sync_step_mode                      (i_sync_step_mode              ),
	                                        
    .iv_link_delay                         (iv_link_delay                 ),
	.iv_link_delay_port_id                 (iv_link_delay_port_id         ),
	.i_link_delay_wr                       (i_link_delay_wr               ),
                                            
	.iv_csrateoffset_localnode             (iv_csrateoffset_localnode ),
    .ov_csrateoffset_previousnode          (ov_csrateoffset_previousnode  ),
    .o_csrateoffset_previousnode_wr        (o_csrateoffset_previousnode_wr),
	                                        
    .iv_data                               (iv_data                       ),
	.i_data_wr                             (i_data_wr                     ),
    .iv_tsmp_subtype                       (iv_tsmp_subtype               ),
 
	.ov_data                               (wv_data_lda2other             ),
	.o_data_wr                             (w_data_wr_lda2other           ),
    .ov_sync_correctfield_time             (wv_sync_correctfield_time_lda2tex),
    .ov_sync_link_delay                    (wv_sync_link_delay_lda2tex       )
);

time_extract time_extract_inst
(
    .i_clk                                 (i_clk                          ),
    .i_rst_n                               (i_rst_n                        ),
    
    .i_sync_step_mode                      (i_sync_step_mode               ),
    
    .iv_data                               (wv_data_lda2other              ),
	.i_data_wr                             (w_data_wr_lda2other            ),
    .iv_sync_correctfield_time             (wv_sync_correctfield_time_lda2tex),
    .iv_sync_link_delay                    (wv_sync_link_delay_lda2tex       ),	                                        
	//.ov_cumulativescaledrateoffset         (ov_cumulativescaledrateoffset  ),
	//.o_cumulativescaledrateoffset_wr       (o_cumulativescaledrateoffset_wr),
	                                        
    .ov_gm_timestamps                      (ov_gm_timestamps              ),
	.ov_correctfield_time                  (ov_correctfield_time          ),
	.ov_local_cnt_rx                       (ov_local_cnt_rx               ),
    .ov_sync_correctfield_time             (ov_sync_correctfield_time),
    .ov_sync_link_delay                    (ov_sync_link_delay       ),
	.o_time_info_valid                     (o_time_info_valid             ) 
);

sync_transmit_select sync_transmit_select_inst
(
    .i_clk                 (i_clk                ),
    .i_rst_n               (i_rst_n              ),
                            
	.i_tsnnic_or_tsnswitch (i_tsnnic_or_tsnswitch),//1:tsnnic.  0:tsnswitch
                            
    .iv_data               (wv_data_lda2other    ),
	.i_data_wr             (w_data_wr_lda2other  ),	
                            
	.ov_data               (ov_data              ),
	.o_data_wr             (o_data_wr            )
);

clock_correct_calculate#(.clk_period(clk_period)) clock_correct_calculate_inst
(
    .i_clk                                 (i_clk  ),
    .i_rst_n                               (i_rst_n),
 
    .iv_gm_timestamps                      (ov_gm_timestamps    ),
	.iv_correctfield_time                  (ov_correctfield_time),
	.iv_local_cnt_rx                       (ov_local_cnt_rx     ),
	.i_time_info_valid                     (o_time_info_valid   ),
 
	.iv_local_count                        (ov_local_count     ),
	.iv_offset_threshold                   (iv_offset_threshold),
	.iv_sync_clk                           (wv_sync_clk_ctc2ccc[120:25]        ),
 
	.ov_clk_set                            (ov_clk_set            ),
	.o_clk_set_wr                          (o_clk_set_wr          ),
    .ov_current_local_count                (ov_current_local_count),
    .ov_current_sync_clk                   (ov_current_sync_clk   ),
 
	.o_sync_ok                             (o_sync_ok             ),
    .o_sync_ok_wr                          (o_sync_ok_wr          ),	
    .ov_offset                             (ov_offset             ),
	.o_offset_wr                           (o_offset_wr           ),
    .ov_offset_abnormal_cnt                (ov_offset_abnormal_cnt),	
	.o_sync_result_wr                      (o_sync_result_wr      )
    	
);

clock_timing_and_correcting #(.clk_period(clk_period))clock_timing_and_correcting_inst
(
        .i_clk                  (i_clk   ),
        .i_rst_n                (i_rst_n ),
	 
        .iv_syn_clock_set       (ov_clk_set  ),
        .i_syn_clock_set_wr     (o_clk_set_wr),
	 
        .iv_frequency_cor       (iv_frequency_cor    ),
        .i_frequency_cor_wr     (i_frequency_cor_wr  ),
 
        .ov_complete_clk        (wv_sync_clk_ctc2ccc ),
        .ov_frequency_cor       (ov_frequency_cor    )
);

local_cnt_timing#(.clk_period(clk_period))//#(.clk_period(clk_period))  
local_cnt_timing_inst
(
        .i_clk          (i_clk  ),
        .i_rst_n        (i_rst_n),
 
		.o_local_cnt_rst(o_local_cnt_rst     ),
        .ov_local_cnt   (ov_local_count)
);
endmodule